Recent advances in computing technology have enabled computer system designers to efficiently integrate multiple processor cores into a single chip. At present, dual-core processor systems are commonplace, and quad-core processor systems are going to dominate in the next couple of years. Extrapolating forward several years, the technology roadmap for virtually every processor manufacturer indicates significant growth in the number of processor cores in computer systems. Hence, computer systems are likely to include 64, 128, 256, or even 512 processor cores in the not-too-distant future.
However, as larger numbers of processor cores attempt to access a computer's memory system, conflicts are likely to arise. More specifically, because processor cores generally run different programs, their memory reference patterns are generally uncorrelated. This lack of correlation is not a problem for computer systems that have a small number of processor cores and a large number of memory banks, because the likelihood of two or more processor cores accessing the same memory banks is small on average when the number of banks is much larger than the number of processor cores. Hence, references from a given processor core are unlikely to encounter open pages from another processor core. The rows which are accessed by a given processor core are likely to be already open to service preceding references from the given processor core, which means that memory references are likely to generate page-hits.
However, as the number of processor cores increases, the number of software threads is likely to increase proportionately, and with more threads comes more interference. The likelihood of a thread interfering with another thread is likely to increase significantly with the number of threads for a given number of banks in the memory system. For example, instead of keeping a page open to service multiple column accesses from the same processor core to take advantage of spatial locality in reference streams, an access from another processor core can disrupt the memory access stream and cause the page to be closed and a new page to be opened. These additional page operations cause additional precharge and activate operations, and can lead to wasted power and lower efficiency for the memory system.